driver-api/cxl/memory-devices.rst

1 .. SPDX-License-Identifier: GPL-2.0
13 that optionally define a device's contribution to an interleaved address
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
43     # cxl list -BEMPu -b cxl_test
185 its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
195 objects. Conversely for hot-unplug / removal scenarios, there is no need for
196 the Linux PCI core to tear down switch-level CXL resources because the endpoint
197 ->remove() event cleans up the port data that was established to support that
203     # cxl list -BDMu -d root -m mem3
261     # cxl list -MDu -d 3.2
320 -----------------
322 .. kernel-doc:: drivers/cxl/pci.c
325 .. kernel-doc:: drivers/cxl/pci.c
328 .. kernel-doc:: drivers/cxl/mem.c
331 .. kernel-doc:: drivers/cxl/cxlmem.h
334 .. kernel-doc:: drivers/cxl/core/memdev.c
338 --------
339 .. kernel-doc:: drivers/cxl/port.c
343 --------
344 .. kernel-doc:: drivers/cxl/cxl.h
347 .. kernel-doc:: drivers/cxl/cxl.h
350 .. kernel-doc:: drivers/cxl/core/hdm.c
353 .. kernel-doc:: drivers/cxl/core/hdm.c
356 .. kernel-doc:: drivers/cxl/core/cdat.c
359 .. kernel-doc:: drivers/cxl/core/port.c
362 .. kernel-doc:: drivers/cxl/core/port.c
365 .. kernel-doc:: drivers/cxl/core/pci.c
368 .. kernel-doc:: drivers/cxl/core/pci.c
371 .. kernel-doc:: drivers/cxl/core/pmem.c
374 .. kernel-doc:: drivers/cxl/core/regs.c
377 .. kernel-doc:: drivers/cxl/core/mbox.c
381 -----------
382 .. kernel-doc:: drivers/cxl/core/region.c
385 .. kernel-doc:: drivers/cxl/core/region.c
392 -------------------
394 .. kernel-doc:: include/uapi/linux/cxl_mem.h
397 .. kernel-doc:: include/uapi/linux/cxl_mem.h