bindings/usb/ti%2Cj721e-usb.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI wrapper module for the Cadence USBSS-DRD controller
10   - Roger Quadros <rogerq@kernel.org>
15       - const: ti,j721e-usb
16       - items:
17           - const: ti,am64-usb
18           - const: ti,j721e-usb
25   power-domains:
29       Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
37   clock-names:
39       - const: ref
40       - const: lpm
42   ti,usb2-only:
45       operation. Must be present if USB3 PHY is not available
49   ti,vbus-divider:
55   '#address-cells':
58   '#size-cells':
61   dma-coherent: true
68   - compatible
69   - reg
70   - power-domains
71   - clocks
72   - clock-names
77   - |
78     #include <dt-bindings/soc/ti,sci_pm_domain.h>
79     #include <dt-bindings/interrupt-controller/arm-gic.h>
82         #address-cells = <2>;
83         #size-cells = <2>;
86             compatible = "ti,j721e-usb";
88             power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
90             clock-names = "ref", "lpm";
91             assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
92             assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
93             #address-cells = <2>;
94             #size-cells = <2>;
97                   compatible = "cdns,usb3";
101                   reg-names = "otg", "xhci", "dev";
105                   interrupt-names = "host",
107                                     "otg";
108                   maximum-speed = "super-speed";
109                   dr_mode = "otg";