Lines Matching +full:rx +full:- +full:thr +full:- +full:num +full:- +full:pkt
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
36 - const: synopsys,dwc3
49 interrupt-names:
53 - const: dwc_usb3
54 - items:
65 clock-names:
68 - enum: [bus_early, ref, suspend]
69 - true
71 dma-coherent: true
80 usb-phy:
83 - description: USB2/HS PHY
84 - description: USB3/SS PHY
90 phy-names:
94 - items:
95 enum: [ usb2-phy, usb3-phy ]
96 - items:
97 pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
99 power-domains:
101 The DWC3 has 2 power-domains. The power management unit (PMU) and
106 - description: Core
107 - description: Power management unit
112 snps,usb2-lpm-disable:
121 snps,usb2-gadget-lpm-disable:
126 snps,dis-start-transfer-quirk:
128 When set, disable isoc START TRANSFER command failure SW work-around
129 for DWC_usb31 version 1.70a-ea06 and prior.
138 snps,has-lpm-erratum:
142 snps,lpm-nyet-threshold:
176 RX.Detect.
180 description: When set core will set Tx de-emphasis value
189 - 0 # -6dB de-emphasis
190 - 1 # -3.5dB de-emphasis
191 - 2 # No de-emphasis
207 snps,dis-u1-entry-quirk:
211 snps,dis-u2-entry-quirk:
220 snps,dis-u2-freeclk-exists-quirk:
223 PHY doesn't provide a free-running PHY clock.
226 snps,dis-del-phy-power-chg-quirk:
231 snps,dis-tx-ipgap-linecheck-quirk:
235 snps,parkmode-disable-ss-quirk:
240 snps,parkmode-disable-hs-quirk:
251 snps,dis-split-quirk:
254 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
257 snps,gfladj-refclk-lpm-sel-quirk:
262 snps,resume-hs-terminations:
269 snps,ulpi-ext-vbus-drv:
277 snps,is-utmi-l1-suspend:
283 snps,hird-threshold:
289 High-Speed PHY interface selection between UTMI+ and ULPI when the
294 snps,quirk-frame-length-adjustment:
296 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
303 snps,ref-clock-period-ns:
314 snps,rx-thr-num-pkt:
316 USB RX packet threshold count. In host mode, this field specifies
317 the space that must be available in the RX FIFO before the core can
318 start the corresponding USB RX transaction (burst).
320 available in the RX FIFO before the core can send ERDY for a
321 flow-controlled endpoint. It is only used for SuperSpeed.
328 snps,rx-max-burst:
330 Max USB RX burst size. In host mode, this field specifies the
332 bus is slower than the USB, RX FIFO can overrun during a long burst.
333 You can program a smaller value to this field to limit the RX burst
344 snps,tx-thr-num-pkt:
357 snps,tx-max-burst:
370 snps,rx-thr-num-pkt-prd:
372 Periodic ESS RX packet threshold count (host mode only). Set this and
373 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
374 programming guide section 1.2.4) to enable periodic ESS RX threshold.
379 snps,rx-max-burst-prd:
381 Max periodic ESS RX burst size (host mode only). Set this and
382 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
383 programming guide section 1.2.4) to enable periodic ESS RX threshold.
388 snps,tx-thr-num-pkt-prd:
391 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
397 snps,tx-max-burst-prd:
400 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
406 tx-fifo-resize:
414 tx-fifo-max-num:
422 snps,incr-burst-type-adjustment:
429 $ref: /schemas/types.yaml#/definitions/uint32-array
436 num-hc-interrupters:
443 This port is used with the 'usb-role-switch' property to connect the
450 controller using the OF graph bindings specified if the "usb-role-switch"
462 wakeup-source:
470 - compatible
471 - reg
472 - interrupts
475 - |
480 usb-phy = <&usb2_phy>, <&usb3_phy>;
481 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
483 - |
489 clock-names = "bus_early", "ref", "suspend";
491 phy-names = "usb2-phy", "usb3-phy";