Lines Matching full:bpmp
148 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
149 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
150 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
151 <&bpmp TEGRA194_CLK_XUSB_SS>,
152 <&bpmp TEGRA194_CLK_CLK_M>,
153 <&bpmp TEGRA194_CLK_XUSB_FS>,
154 <&bpmp TEGRA194_CLK_UTMIPLL>,
155 <&bpmp TEGRA194_CLK_CLK_M>,
156 <&bpmp TEGRA194_CLK_PLLE>;
166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
167 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;