bindings/timer/riscv%2Ctimer.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10   - Anup Patel <anup@brainfault.org>
13   RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14   based on the time CSR defined by the RISC-V privileged specification. The
15   timer interrupts of this device are configured using the RISC-V SBI Time
16   extension or the RISC-V Sstc extension.
18   The clock frequency of RISC-V timer device is specified via the
19   "timebase-frequency" DT property of "/cpus" DT node which is described
25       - riscv,timer
27   interrupts-extended:
31   riscv,timer-cannot-wake-cpu:
34       If present, the timer interrupt cannot wake up the CPU from one or
40   - compatible
41   - interrupts-extended
44   - |
45     timer {
46       compatible = "riscv,timer";
47       interrupts-extended = <&cpu1intc 5>,