bindings/spmi/qcom%2Cx1e80100-spmi-pmic-arb.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)
10   - Stephen Boyd <sboyd@kernel.org>
13   The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI
14   controller with wrapping arbitration logic to allow for multiple on-chip
15   devices to control up to 2 SPMI separate buses.
17   The PMIC Arbiter can also act as an interrupt controller, providing interrupts
22     const: qcom,x1e80100-spmi-pmic-arb
26       - description: core registers
27       - description: tx-channel per virtual slave registers
28       - description: rx-channel (called observer) per virtual slave registers
30   reg-names:
32       - const: core
33       - const: chnls
34       - const: obsrvr
38   '#address-cells':
41   '#size-cells':
56       which of the PMIC Arb provided channels to use for accesses
59   "^spmi@[a-f0-9]+$":
61     $ref: /schemas/spmi/spmi.yaml
67           - description: configuration registers
68           - description: interrupt controller registers
70       reg-names:
72           - const: cnfg
73           - const: intr
78       interrupt-names:
81       interrupt-controller: true
83       '#interrupt-cells':
86           cell 1: slave ID for the requested interrupt (0-15)
87           cell 2: peripheral ID for requested interrupt (0-255)
88           cell 3: the requested peripheral interrupt (0-7)
89           cell 4: interrupt flags indicating level-sense information,
90                   as defined in dt-bindings/interrupt-controller/irq.h
93   - compatible
94   - reg-names
95   - qcom,ee
96   - qcom,channel
101   - |
102     #include <dt-bindings/interrupt-controller/arm-gic.h>
105       #address-cells = <2>;
106       #size-cells = <2>;
108       spmi: arbiter@c400000 {
109         compatible = "qcom,x1e80100-spmi-pmic-arb";
113         reg-names = "core", "chnls", "obsrvr";
118         #address-cells = <2>;
119         #size-cells = <2>;
122         spmi_bus0: spmi@c42d000 {
125           reg-names = "cnfg", "intr";
127           interrupt-names = "periph_irq";
128           interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
129           interrupt-controller;
130           #interrupt-cells = <4>;
132           #address-cells = <2>;
133           #size-cells = <0>;