Lines Matching +full:tegra20 +full:- +full:car
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20/30 SLINK controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-slink
17 - nvidia,tegra30-slink
27 - description: module clock
31 - description: module reset
33 reset-names:
35 - const: spi
39 - description: DMA channel used for reception
40 - description: DMA channel used for transmission
42 dma-names:
44 - const: rx
45 - const: tx
47 operating-points-v2:
50 power-domains:
52 - description: phandle to the core power domain
54 spi-max-frequency:
59 - $ref: spi-controller.yaml
64 - compatible
65 - reg
66 - interrupts
67 - clocks
68 - resets
69 - reset-names
70 - dmas
71 - dma-names
74 - |
75 #include <dt-bindings/clock/tegra20-car.h>
76 #include <dt-bindings/interrupt-controller/arm-gic.h>
79 compatible = "nvidia,tegra20-slink";
82 spi-max-frequency = <25000000>;
83 #address-cells = <1>;
84 #size-cells = <0>;
87 reset-names = "spi";
89 dma-names = "rx", "tx";