bindings/sound/rockchip%2Crk3308-codec.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,rk3308-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3308 Internal Codec
10   This is the audio codec embedded in the Rockchip RK3308
11   SoC. It has 8 24-bit ADCs and 2 24-bit DACs. The maximum supported
17   The RK3308 audio codec has 8 independent capture channels, but some
19     * grp 0 -- MIC1 / MIC2
20     * grp 1 -- MIC3 / MIC4
21     * grp 2 -- MIC5 / MIC6
22     * grp 3 -- MIC7 / MIC8
25   - Luca Ceresoli <luca.ceresoli@bootlin.com>
29     const: rockchip,rk3308-codec
41       - description: clock for TX
42       - description: clock for RX
43       - description: AHB clock driving the interface
45   clock-names:
47       - const: mclk_tx
48       - const: mclk_rx
49       - const: hclk
52     $ref: audio-graph-port.yaml#
58   reset-names:
60       - const: codec
62   "#sound-dai-cells":
65   rockchip,micbias-avdd-percent:
70       E.g. if rockchip,micbias-avdd-percent = 85 and AVDD = 3v3, then the
76   - compatible
77   - reg
78   - rockchip,grf
79   - clocks
80   - resets
81   - "#sound-dai-cells"
86   - |
87     #include <dt-bindings/clock/rk3308-cru.h>
89     audio_codec: audio-codec@ff560000 {
90         compatible = "rockchip,rk3308-codec";
93         clock-names = "mclk_tx", "mclk_rx", "hclk";
94         clocks = <&cru SCLK_I2S2_8CH_TX_OUT>,
95                  <&cru SCLK_I2S2_8CH_RX_OUT>,
96                  <&cru PCLK_ACODEC>;
97         reset-names = "codec";
98         resets = <&cru SRST_ACODEC_P>;
99         #sound-dai-cells = <0>;