Lines Matching +full:0 +full:x702d0000

82         assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
98         reg = <0x702d0800 0x800>;
105         ranges = <0x702d0000 0x702d0000 0x0000e400>;
109             #size-cells = <0>;
111             port@0 {
112                 reg = <0x0>;
121                 reg = <0xa>;
130             reg = <0x702d0000 0x800>;
154                 #size-cells = <0>;
156                 admaif1_port: port@0 {
157                     reg = <0x0>;
174             reg = <0x702d1000 0x100>;
178                 #size-cells = <0>;
180                 port@0 {
181                     reg = <0x0>;
189                     reg = <0x1>;