Lines Matching full:cirrus

5   - compatible : "cirrus,cs35l33"
21   - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
26   - cirrus,ramp-rate : On power up, it affects the time from when the power
34   - cirrus,boost-ipk : The maximum current allowed for the boost converter.
38   - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON
45 The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
48   - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that
51 Optional properties for the "cirrus,hg-algo" sub-node:
53   - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in
57     cirrus,release-rate : The number of consecutive LRCLK periods before
61   - cirrus,ldo-thld : Configures the signal threshold at which the PWM output
66   - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G
70   - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G
75   - cirrus,vp-hg-auto : This is a boolean property.  When set, class H/G VPhg
78   - cirrus,vp-hg :  Class H/G algorithm VPhg.  Controls the H/G algorithm's
83   - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
89   - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking
97 	compatible = "cirrus,cs35l33";
108 	cirrus,ramp-rate = <0x0>;
109 	cirrus,boost-ctl = <0x30>;  /* VBST = 8000mV */
110 	cirrus,boost-ipk = <0xE0>; /* 3600mA */
111 	cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */
113 	cirrus,hg-algo {
114 		cirrus,mem-depth = <0x3>;
115 		cirrus,release-rate = <0x3>;
116 		cirrus,ldo-thld = <0x1>;
117 		cirrus,ldo-path-disable = <0x0>;
118 		cirrus,ldo-entry-delay=<0x4>;
119 		cirrus,vp-hg-auto;
120 		cirrus,vp-hg=<0xF>;
121 		cirrus,vp-hg-rate=<0x2>;
122 		cirrus,vp-hg-va=<0x0>;