Lines Matching +full:0 +full:x34000
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
317 "^(pru|rtu|txpru)@[0-9a-f]+$":
370 pruss: pruss@0 {
372 reg = <0x0 0x80000>;
377 pruss_mem: memories@0 {
378 reg = <0x0 0x2000>,
379 <0x2000 0x2000>,
380 <0x10000 0x3000>;
388 reg = <0x26000 0x2000>;
389 ranges = <0x00 0x26000 0x2000>;
393 #size-cells = <0>;
396 reg = <0x30>;
397 #clock-cells = <0>;
406 reg = <0x32000 0x58>;
411 reg = <0x20000 0x2000>;
423 reg = <0x34000 0x2000>,
424 <0x22000 0x400>,
425 <0x22400 0x100>;
432 reg = <0x38000 0x2000>,
433 <0x24000 0x400>,
434 <0x24400 0x100>;
441 reg = <0x32400 0x90>;
446 #size-cells = <0>;
454 pruss1: pruss@0 {
456 reg = <0x0 0x40000>;
461 pruss1_mem: memories@0 {
462 reg = <0x0 0x2000>,
463 <0x2000 0x2000>,
464 <0x10000 0x8000>;
472 reg = <0x26000 0x2000>;
473 ranges = <0x00 0x26000 0x2000>;
477 #size-cells = <0>;
480 reg = <0x30>;
481 #clock-cells = <0>;
490 reg = <0x32000 0x58>;
495 reg = <0x20000 0x2000>;
509 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
514 reg = <0x34000 0x3000>,
515 <0x22000 0x400>,
516 <0x22400 0x100>;
523 reg = <0x38000 0x3000>,
524 <0x24000 0x400>,
525 <0x24400 0x100>;
532 reg = <0x32400 0x90>;
537 #size-cells = <0>;