Lines Matching +full:0 +full:x4140

48   "^mux-controller@[0-9a-f]+$":
53   "^clock-controller@[0-9a-f]+$":
59   "phy@[0-9a-f]+$":
65   "^chipid@[0-9a-f]+$":
84         reg = <0x00100000 0x1c000>;
91             reg = <0x00004080 0x50>;
95                 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96                 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97                 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98                 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
99                 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
105             reg = <0x4140 0x18>;
111             reg = <0x14 0x4>;