Lines Matching +full:power +full:- +full:on
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
20 - nvidia,tegra210-pmc
25 clock-names:
28 - const: pclk
30 - const: clk32k_in
35 '#clock-cells':
43 include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
45 '#interrupt-cells':
50 interrupt-controller: true
52 nvidia,invert-interrupt:
54 description: Inverts the PMU interrupt signal. The PMU is an external Power
60 nvidia,core-power-req-active-high:
62 description: core power request active-high
64 nvidia,sys-clock-req-active-high:
66 description: system clock request active-high
68 nvidia,combined-power-req:
70 description: combined power request for CPU and core
72 nvidia,cpu-pwr-good-en:
74 description: CPU power good signal from external PMIC to PMC is enabled
76 nvidia,suspend-mode:
80 - description: LP0, CPU + Core voltage off and DRAM in self-refresh
82 - description: LP1, CPU voltage off and DRAM in self-refresh
84 - description: LP2, CPU voltage off
87 nvidia,cpu-pwr-good-time:
89 description: CPU power good time in microseconds
91 nvidia,cpu-pwr-off-time:
93 description: CPU power off time in microseconds
95 nvidia,core-pwr-good-time:
96 $ref: /schemas/types.yaml#/definitions/uint32-array
97 description: core power good time in microseconds
99 - description: oscillator stable time
100 - description: power stable time
102 nvidia,core-pwr-off-time:
104 description: core power off time in microseconds
106 nvidia,lp0-vec:
107 $ref: /schemas/types.yaml#/definitions/uint32-array
111 The AVP (Audio-Video Processor) is an ARM7 processor and always being
112 the first boot processor when chip is power on or resume from deep sleep
117 - description: starting address of LP0 vector
118 - description: length of LP0 vector
120 core-supply:
121 description: phandle to voltage regulator connected to the SoC core power
124 core-domain:
127 core power domain, which has a dedicated voltage rail that powers the
131 operating-points-v2:
132 description: Should contain level, voltages and opp-supported-hw
133 property. The supported-hw is a bitfield indicating SoC speedo or
136 "#power-domain-cells":
140 - operating-points-v2
141 - "#power-domain-cells"
143 i2c-thermtrip:
145 description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
146 exists, hardware-triggered thermal reset will be enabled.
149 nvidia,i2c-controller-id:
155 nvidia,bus-addr:
157 description: bus address of the PMU on the I2C bus
159 nvidia,reg-addr:
163 nvidia,reg-data:
165 description: power-off command to write to PMU
167 nvidia,pinmux-id:
169 description: Pinmux used by the hardware when issuing power-off command.
174 - nvidia,i2c-controller-id
175 - nvidia,bus-addr
176 - nvidia,reg-addr
177 - nvidia,reg-data
183 This node contains a hierarchy of power domain nodes, which should match
184 the powergates on the Tegra SoC. Each powergate node represents a power-
185 domain on the Tegra SoC that can be power-gated by the Tegra PMC.
187 Hardware blocks belonging to a power domain should contain "power-domains"
194 Please refer to Tegra TRM for mode details on the powergate nodes to use
195 for each power-gate block inside Tegra.
198 --------------------------------------------------------------
223 "^[a-z0-9]+$":
235 power-domains:
238 '#power-domain-cells':
243 - clocks
244 - resets
245 - '#power-domain-cells'
252 This is a pad configuration node. On Tegra SoCs a pad is a set of pins
254 of the hardware. The PMC can be used to set pad power state and
255 signaling voltage. A pad can be either in active or power down mode.
256 The support for power state and signaling voltage configuration varies
257 depending on the pad in question. 3.3V and 1.8V signaling voltages are
258 supported on pins where software controllable signaling voltage
265 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
270 The following pads are present on Tegra124 and Tegra132:
273 hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
274 pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
277 The following pads are present on Tegra210:
279 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
280 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
281 hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
282 sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
286 $ref: /schemas/types.yaml#/definitions/string-array
289 low-power-enable:
291 description: Configure the pad into power down mode.
293 low-power-disable:
297 power-source:
304 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
306 Power state can be configured on all Tegra124 and Tegra132 pads.
308 switching. All of the listed Tegra210 pads except pex-cntrl support
309 power state configuration. Signaling voltage switching is supported
310 on the following Tegra210 pads:
312 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
313 spi, spi-hv, uart
316 - pins
319 - compatible
320 - reg
321 - clock-names
322 - clocks
323 - '#clock-cells'
326 - if:
330 const: nvidia,tegra124-pmc
340 dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
341 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
345 - if:
349 const: nvidia,tegra210-pmc
358 enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
359 csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
360 dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
361 pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
362 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
363 usb-bias ]
368 nvidia,suspend-mode: ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
369 nvidia,core-pwr-off-time: ["nvidia,core-pwr-good-time"]
370 nvidia,cpu-pwr-off-time: ["nvidia,cpu-pwr-good-time"]
373 - |
374 #include <dt-bindings/clock/tegra210-car.h>
375 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
376 #include <dt-bindings/soc/tegra-pmc.h>
379 compatible = "nvidia,tegra210-pmc";
381 core-supply = <®ulator>;
383 clock-names = "pclk", "clk32k_in";
384 #clock-cells = <1>;
386 nvidia,invert-interrupt;
387 nvidia,suspend-mode = <0>;
388 nvidia,cpu-pwr-good-time = <0>;
389 nvidia,cpu-pwr-off-time = <0>;
390 nvidia,core-pwr-good-time = <4587 3876>;
391 nvidia,core-pwr-off-time = <39065>;
392 nvidia,core-power-req-active-high;
393 nvidia,sys-clock-req-active-high;
395 pd_core: core-domain {
396 operating-points-v2 = <&core_opp_table>;
397 #power-domain-cells = <0>;
405 power-domains = <&pd_core>;
406 #power-domain-cells = <0>;
412 power-domains = <&pd_core>;
413 #power-domain-cells = <0>;