Lines Matching +full:14 +full:a

14   a sideband logic handling signals to DWC3 host controller inside
41   "^reset-controller@[0-9a-f]+$":
44   "^regulator@[0-9a-f]+$":
47   "^phy@[0-9a-f]+$":
72             clocks = <&sys_clk 14>;
74             resets = <&sys_rst 14>;
81             clocks = <&sys_clk 14>;
83             resets = <&sys_rst 14>;
91             clocks = <&sys_clk 14>, <&sys_clk 16>;
93             resets = <&sys_rst 14>, <&sys_rst 16>;
101             clocks = <&sys_clk 14>, <&sys_clk 18>;
103             resets = <&sys_rst 14>, <&sys_rst 18>;