fsl/cpm_qe/fsl%2Cucc-hdlc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
12   - Frank Li <Frank.Li@nxp.com>
16     const: fsl,ucc-hdlc
24   cell-index:
27   rx-clock-name:
30       - pattern: "^brg([0-9]|1[0-6])$"
31       - pattern: "^clk([0-9]|1[0-9]|2[0-4])$"
33   tx-clock-name:
36       - pattern: "^brg([0-9]|1[0-6])$"
37       - pattern: "^clk([0-9]|1[0-9]|2[0-4])$"
39   fsl,tdm-interface:
40     $ref: /schemas/types.yaml#/definitions/flag
41     description: Specify that hdlc is based on tdm-interface
43   fsl,rx-sync-clock:
45     description: rx-sync
47       - none
48       - rsync_pin
49       - brg9
50       - brg10
51       - brg11
52       - brg13
53       - brg14
54       - brg15
56   fsl,tx-sync-clock:
58     description: tx-sync
60       - none
61       - tsync_pin
62       - brg9
63       - brg10
64       - brg11
65       - brg13
66       - brg14
67       - brg15
69   fsl,tdm-framer-type:
74   fsl,tdm-id:
78   fsl,tx-timeslot-mask:
85   fsl,rx-timeslot-mask:
92   fsl,siram-entry-id:
98   fsl,tdm-internal-loopback:
99     $ref: /schemas/types.yaml#/definitions/flag
112   - compatible
113   - reg
118   - |
120         compatible = "fsl,ucc-hdlc";
122         rx-clock-name = "clk8";
123         tx-clock-name = "clk9";
124         fsl,rx-sync-clock = "rsync_pin";
125         fsl,tx-sync-clock = "tsync_pin";
126         fsl,tx-timeslot-mask = <0xfffffffe>;
127         fsl,rx-timeslot-mask = <0xfffffffe>;
128         fsl,tdm-framer-type = "e1";
129         fsl,tdm-id = <0>;
130         fsl,siram-entry-id = <0>;
131         fsl,tdm-interface;
134   - |
136         compatible = "fsl,ucc-hdlc";
138         rx-clock-name = "brg1";
139         tx-clock-name = "brg1";