fsl/cpm_qe/fsl%2Cqe-ucc-qmc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Herve Codina <herve.codina@bootlin.com>
19       - enum:
20           - fsl,mpc8321-ucc-qmc
21       - const: fsl,qe-ucc-qmc
25       - description: UCC (Unified communication controller) register base
26       - description: Dual port ram base
28   reg-names:
30       - const: ucc_regs
31       - const: dpram
37   fsl,tsa-serial:
38     $ref: /schemas/types.yaml#/definitions/phandle-array
40       - items:
41           - description: phandle to TSA node
42           - enum: [1, 2, 3, 4, 5]
44               TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these
46                - 1: UCC1
47                - 2: UCC2
48                - 3: UCC3
49                - 4: UCC4
50                - 5: UCC5
55   fsl,soft-qmc:
61   '#address-cells':
64   '#size-cells':
68   '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
77           - enum:
78               - fsl,mpc8321-ucc-qmc-hdlc
79           - const: fsl,qe-ucc-qmc-hdlc
80           - const: fsl,qmc-hdlc
88       fsl,operational-mode:
94             - hdlc: The channel handles HDLC frames
95             - transparent: The channel handles raw data without any processing
97       fsl,reverse-data:
104       fsl,tx-ts-mask:
107           Channel assigned Tx time-slots within the Tx time-slots routed by the
110       fsl,rx-ts-mask:
113           Channel assigned Rx time-slots within the Rx time-slots routed by the
124       - if:
129                   const: fsl,qmc-hdlc
135       - reg
136       - fsl,tx-ts-mask
137       - fsl,rx-ts-mask
140   - compatible
141   - reg
142   - reg-names
143   - interrupts
144   - fsl,tsa-serial
145   - '#address-cells'
146   - '#size-cells'
151   - |
152     #include <dt-bindings/soc/qe-fsl,tsa.h>
155         compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";
158         reg-names = "ucc_regs", "dpram";
160         interrupt-parent = <&qeic>;
161         fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin";
163         #address-cells = <1>;
164         #size-cells = <0>;
166         fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>;
171             fsl,operational-mode = "transparent";
172             fsl,reverse-data;
173             fsl,tx-ts-mask = <0x00000000 0x000000aa>;
174             fsl,rx-ts-mask = <0x00000000 0x000000aa>;
180             fsl,operational-mode = "transparent";
181             fsl,reverse-data;
182             fsl,tx-ts-mask = <0x00000000 0x00000055>;
183             fsl,rx-ts-mask = <0x00000000 0x00000055>;
188             compatible = "fsl,mpc8321-ucc-qmc-hdlc",
189                          "fsl,qe-ucc-qmc-hdlc",
190                          "fsl,qmc-hdlc";
192             fsl,operational-mode = "hdlc";
193             fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
194             fsl,rx-ts-mask = <0x00000000 0x0000ff00>;