fsl/cpm_qe/fsl%2Ccpm1-scc-qmc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Herve Codina <herve.codina@bootlin.com>
19       - enum:
20           - fsl,mpc885-scc-qmc
21           - fsl,mpc866-scc-qmc
22       - const: fsl,cpm1-scc-qmc
26       - description: SCC (Serial communication controller) register base
27       - description: SCC parameter ram base
28       - description: Dual port ram base
30   reg-names:
32       - const: scc_regs
33       - const: scc_pram
34       - const: dpram
40   fsl,tsa-serial:
41     $ref: /schemas/types.yaml#/definitions/phandle-array
43       - items:
44           - description: phandle to TSA node
45           - enum: [1, 2, 3]
47               TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these
49                - 1: SCC2
50                - 2: SCC3
51                - 3: SCC4
56   '#address-cells':
59   '#size-cells':
63   '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
76       fsl,operational-mode:
82             - hdlc: The channel handles HDLC frames
83             - transparent: The channel handles raw data without any processing
85       fsl,reverse-data:
92       fsl,tx-ts-mask:
95           Channel assigned Tx time-slots within the Tx time-slots routed by the
98       fsl,rx-ts-mask:
101           Channel assigned Rx time-slots within the Rx time-slots routed by the
106           - enum:
107               - fsl,mpc885-scc-qmc-hdlc
108               - fsl,mpc866-scc-qmc-hdlc
109           - const: fsl,cpm1-scc-qmc-hdlc
110           - const: fsl,qmc-hdlc
120       - if:
125                   const: fsl,qmc-hdlc
131       - reg
132       - fsl,tx-ts-mask
133       - fsl,rx-ts-mask
136   - compatible
137   - reg
138   - reg-names
139   - interrupts
140   - fsl,tsa-serial
141   - '#address-cells'
142   - '#size-cells'
147   - |
148     #include <dt-bindings/soc/cpm1-fsl,tsa.h>
151         compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
155         reg-names = "scc_regs", "scc_pram", "dpram";
157         interrupt-parent = <&CPM_PIC>;
159         #address-cells = <1>;
160         #size-cells = <0>;
162         fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;
167             fsl,operational-mode = "transparent";
168             fsl,reverse-data;
169             fsl,tx-ts-mask = <0x00000000 0x000000aa>;
170             fsl,rx-ts-mask = <0x00000000 0x000000aa>;
176             fsl,operational-mode = "transparent";
177             fsl,reverse-data;
178             fsl,tx-ts-mask = <0x00000000 0x00000055>;
179             fsl,rx-ts-mask = <0x00000000 0x00000055>;
184             compatible = "fsl,mpc885-scc-qmc-hdlc",
185                          "fsl,cpm1-scc-qmc-hdlc",
186                          "fsl,qmc-hdlc";
188             fsl,operational-mode = "hdlc";
189             fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
190             fsl,rx-ts-mask = <0x00000000 0x0000ff00>;