Lines Matching +full:0 +full:x00020000
72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on
76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and
103 either of them can be configured to appear at that R5F's address 0x0.
177 enum: [0, 1]
181 either a value of 1 (enabled) or 0 (disabled), default is disabled
186 enum: [0, 1]
190 either a value of 1 (enabled) or 0 (disabled), default is enabled if
195 enum: [0, 1]
198 address 0 (from core's view). Should be either a value of 1 (ATCM
199 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
234 enum: [0, 2]
247 enum: [0, 1]
274 mailbox0: mailbox-0 {
286 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
287 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
288 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
289 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
295 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
296 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
297 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
298 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
307 ranges = <0x41000000 0x00 0x41000000 0x20000>,
308 <0x41400000 0x00 0x41400000 0x20000>;
312 reg = <0x41000000 0x00008000>,
313 <0x41010000 0x00008000>;
317 ti,sci-proc-ids = <0x01 0xFF>;
331 reg = <0x41400000 0x00008000>,
332 <0x41410000 0x00008000>;
336 ti,sci-proc-ids = <0x02 0xFF>;