bindings/remoteproc/qcom%2Csc7280-wpss-pil.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <bjorn.andersson@linaro.org>
19       - qcom,sc7280-wpss-pil
28       - description: Watchdog interrupt
29       - description: Fatal interrupt
30       - description: Ready interrupt
31       - description: Handover interrupt
32       - description: Stop acknowledge interrupt
33       - description: Shutdown acknowledge interrupt
35   interrupt-names:
37       - const: wdog
38       - const: fatal
39       - const: ready
40       - const: handover
41       - const: stop-ack
42       - const: shutdown-ack
46       - description: GCC WPSS AHB BDG Master clock
47       - description: GCC WPSS AHB clock
48       - description: GCC WPSS RSCP clock
49       - description: XO clock
51   clock-names:
53       - const: ahb_bdg
54       - const: ahb
55       - const: rscp
56       - const: xo
58   power-domains:
60       - description: CX power domain
61       - description: MX power domain
63   power-domain-names:
65       - const: cx
66       - const: mx
70       - description: AOSS restart
71       - description: PDC SYNC
73   reset-names:
75       - const: restart
76       - const: pdc_sync
78   memory-region:
80     description: Reference to the reserved-memory for the Hexagon core
82   firmware-name:
88   qcom,halt-regs:
89     $ref: /schemas/types.yaml#/definitions/phandle-array
94       - items:
95           - description: phandle to TCSR syscon region
96           - description: offset to the Q6 halt register
100     description: Reference to the AOSS side-channel message RAM.
102   qcom,smem-states:
103     $ref: /schemas/types.yaml#/definitions/phandle-array
106       - description: Stop the modem
108   qcom,smem-state-names:
110     const: stop
112   glink-edge:
113     $ref: qcom,glink-edge.yaml#
116       Qualcomm G-Link subnode which represents communication edge, channels
122           - description: IRQ from WPSS to GLINK
126           - description: Mailbox for communication between APPS and WPSS
130           - const: wpss
136   - compatible
137   - reg
138   - interrupts
139   - interrupt-names
140   - clocks
141   - clock-names
142   - power-domains
143   - power-domain-names
144   - resets
145   - reset-names
146   - qcom,halt-regs
147   - memory-region
148   - qcom,qmp
149   - qcom,smem-states
150   - qcom,smem-state-names
151   - glink-edge
156   - |
157     #include <dt-bindings/interrupt-controller/arm-gic.h>
158     #include <dt-bindings/clock/qcom,gcc-sc7280.h>
159     #include <dt-bindings/clock/qcom,rpmh.h>
160     #include <dt-bindings/power/qcom-rpmpd.h>
161     #include <dt-bindings/reset/qcom,sdm845-aoss.h>
162     #include <dt-bindings/reset/qcom,sdm845-pdc.h>
163     #include <dt-bindings/mailbox/qcom-ipcc.h>
165         compatible = "qcom,sc7280-wpss-pil";
168         interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
174         interrupt-names = "wdog", "fatal", "ready", "handover",
175                           "stop-ack", "shutdown-ack";
181         clock-names = "ahb_bdg", "ahb",
184         power-domains = <&rpmhpd SC7280_CX>,
186         power-domain-names = "cx", "mx";
188         memory-region = <&wpss_mem>;
192         qcom,smem-states = <&wpss_smp2p_out 0>;
193         qcom,smem-state-names = "stop";
197         reset-names = "restart", "pdc_sync";
199         qcom,halt-regs = <&tcsr_mutex 0x37000>;
201         glink-edge {
202             interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
209             qcom,remote-pid = <13>;