bindings/regulator/anatop-regulator.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Anatop Voltage Regulators
10   - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13   - $ref: regulator.yaml#
17     const: fsl,anatop-regulator
19   regulator-name: true
21   anatop-reg-offset:
23     description: u32 value representing the anatop MFD register offset.
25   anatop-vol-bit-shift:
27     description: u32 value representing the bit shift for the register.
29   anatop-vol-bit-width:
33   anatop-min-bit-val:
37   anatop-min-voltage:
41   anatop-max-voltage:
45   anatop-delay-reg-offset:
47     description: u32 value representing the anatop MFD step time register offset.
49   anatop-delay-bit-shift:
51     description: u32 value representing the bit shift for the step time register.
53   anatop-delay-bit-width:
57   anatop-enable-bit:
59     description: u32 value representing regulator enable bit offset.
61   vin-supply:
65   - compatible
66   - regulator-name
67   - anatop-reg-offset
68   - anatop-vol-bit-shift
69   - anatop-vol-bit-width
70   - anatop-min-bit-val
71   - anatop-min-voltage
72   - anatop-max-voltage
77   - |
78     regulator-vddpu {
79         compatible = "fsl,anatop-regulator";
80         regulator-name = "vddpu";
81         regulator-min-microvolt = <725000>;
82         regulator-max-microvolt = <1300000>;
83         regulator-always-on;
84         anatop-reg-offset = <0x140>;
85         anatop-vol-bit-shift = <9>;
86         anatop-vol-bit-width = <5>;
87         anatop-delay-reg-offset = <0x170>;
88         anatop-delay-bit-shift = <24>;
89         anatop-delay-bit-width = <2>;
90         anatop-min-bit-val = <1>;
91         anatop-min-voltage = <725000>;
92         anatop-max-voltage = <1300000>;