bindings/pwm/microchip%2Ccorepwm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Conor Dooley <conor.dooley@microchip.com>
16   https://www.microsemi.com/existing-parts/parts/152118
19   - $ref: pwm.yaml#
24       - const: microchip,corepwm-rtl-v4
32   "#pwm-cells":
37   microchip,sync-update-mask:
40       In synchronous mode, all channels are updated at the beginning of the PWM period,
48       Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
49       whether synchronous mode is possible for the PWM channel.
54   microchip,dac-mode-mask:
56       Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
58       cycle. This "DAC" will have far better bandwidth and ripple performance than the
59       standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
61       whether a given channel operates in regular PWM or DAC mode.
62       Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
69   - compatible
70   - reg
71   - clocks
76   - |
77     pwm@41000000 {
78       compatible = "microchip,corepwm-rtl-v4";
79       microchip,sync-update-mask = /bits/ 32 <0>;
82       #pwm-cells = <2>;