Lines Matching +full:soc +full:- +full:s
3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
31 reset that's triggered by one of WDTs. The list is
33 begins from 0 to 3, as keystone can contain up to 4 SoC
38 WDT0 is triggered it issues hard reset for SoC.
40 pllctrl: pll-controller@2310000 {
41 compatible = "ti,keystone-pllctrl", "syscon";
45 devctrl: device-state-control@2620000 {
46 compatible = "ti,keystone-devctrl", "syscon";
50 rstctrl: reset-controller {
51 compatible = "ti,keystone-reset";
52 ti,syscon-pll = <&pllctrl 0xe4>;
53 ti,syscon-dev = <&devctrl 0x328>;
54 ti,wdt-list = <0>;
59 WDT0 or WDT2 is triggered it issues soft reset for SoC.
61 rstctrl: reset-controller {
62 compatible = "ti,keystone-reset";
63 ti,syscon-pll = <&pllctrl 0xe4>;
64 ti,syscon-dev = <&devctrl 0x328>;
65 ti,wdt-list = <0>, <2>;
66 ti,soft-reset;