bindings/pinctrl/qcom%2Cx1e80100-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Rajendra Nayak <quic_rjendra@quicinc.com>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,x1e80100-tlmm
28   gpio-reserved-ranges:
32   gpio-line-names:
36   "-state$":
38       - $ref: "#/$defs/qcom-x1e80100-tlmm-state"
39       - patternProperties:
40           "-pins$":
41             $ref: "#/$defs/qcom-x1e80100-tlmm-state"
45   qcom-x1e80100-tlmm-state:
50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56           List of gpio pins affected by the properties specified in this
57           subnode.
60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
61             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
78                 gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
97       - pins
100   - compatible
101   - reg
106   - |
107     #include <dt-bindings/interrupt-controller/arm-gic.h>
109         compatible = "qcom,x1e80100-tlmm";
111         gpio-controller;
112         #gpio-cells = <2>;
113         gpio-ranges = <&tlmm 0 0 239>;
114         interrupt-controller;
115         #interrupt-cells = <2>;
118         gpio-wo-state {
120             function = "gpio";
123         uart-w-state {
124             rx-pins {
127                 bias-pull-up;
130             tx-pins {
133                 bias-disable;