bindings/pinctrl/qcom%2Csm8450-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Vinod Koul <vkoul@kernel.org>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sm8450-tlmm
28   gpio-reserved-ranges:
32   gpio-line-names:
36   "-state$":
38       - $ref: "#/$defs/qcom-sm8450-tlmm-state"
39       - patternProperties:
40           "-pins$":
41             $ref: "#/$defs/qcom-sm8450-tlmm-state"
45   qcom-sm8450-tlmm-state:
50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56           List of gpio pins affected by the properties specified in this
57           subnode.
60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
61             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
73                 gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
94       - pins
97   - compatible
98   - reg
103   - |
104     #include <dt-bindings/interrupt-controller/arm-gic.h>
106         compatible = "qcom,sm8450-tlmm";
108         gpio-controller;
109         #gpio-cells = <2>;
110         gpio-ranges = <&tlmm 0 0 211>;
111         interrupt-controller;
112         #interrupt-cells = <2>;
115         gpio-wo-state {
117             function = "gpio";
120         uart-w-state {
121             rx-pins {
124                 bias-pull-up;
127             tx-pins {
130                 bias-disable;