bindings/pinctrl/qcom%2Csm8350-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Vinod Koul <vkoul@kernel.org>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sm8350-tlmm
28   gpio-reserved-ranges:
32   gpio-line-names:
36   "-state$":
38       - $ref: "#/$defs/qcom-sm8350-tlmm-state"
39       - patternProperties:
40           "-pins$":
41             $ref: "#/$defs/qcom-sm8350-tlmm-state"
45   qcom-sm8350-tlmm-state:
50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56           List of gpio pins affected by the properties specified in this
57           subnode.
60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"
61             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
74                 gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
95       - pins
98   - compatible
99   - reg
104   - |
105     #include <dt-bindings/interrupt-controller/arm-gic.h>
107         compatible = "qcom,sm8350-tlmm";
110         gpio-controller;
111         #gpio-cells = <2>;
112         interrupt-controller;
113         #interrupt-cells = <2>;
114         gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
116         gpio-wo-subnode-state {
118             function = "gpio";
121         uart-w-subnodes-state {
122             rx-pins {
125                 bias-pull-up;
128             tx-pins {
131                 bias-disable;