bindings/pinctrl/qcom%2Csm6375-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Konrad Dybcio <konradybcio@kernel.org>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sm6375-tlmm
28   gpio-reserved-ranges: true
31   "-state$":
33       - $ref: "#/$defs/qcom-sm6375-tlmm-state"
34       - patternProperties:
35           "-pins$":
36             $ref: "#/$defs/qcom-sm6375-tlmm-state"
40   qcom-sm6375-tlmm-state:
45     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51           List of gpio pins affected by the properties specified in this
52           subnode.
55             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
56             - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
74                 gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
102       - pins
105   - compatible
106   - reg
111   - |
112     #include <dt-bindings/interrupt-controller/arm-gic.h>
114         compatible = "qcom,sm6375-tlmm";
117         gpio-controller;
118         #gpio-cells = <2>;
119         interrupt-controller;
120         #interrupt-cells = <2>;
121         gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */
123         gpio-wo-subnode-state {
125             function = "gpio";
128         uart-w-subnodes-state {
129             rx-pins {
132                 bias-pull-up;
135             tx-pins {
138                 bias-disable;