bindings/pinctrl/qcom%2Csm6350-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Konrad Dybcio <konradybcio@kernel.org>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sm6350-tlmm
29   gpio-reserved-ranges:
33   gpio-line-names:
37   "-state$":
39       - $ref: "#/$defs/qcom-sm6350-tlmm-state"
40       - patternProperties:
41           "-pins$":
42             $ref: "#/$defs/qcom-sm6350-tlmm-state"
46   qcom-sm6350-tlmm-state:
51     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57           List of gpio pins affected by the properties specified in this
58           subnode.
61             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
62             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
77                 dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
99       - pins
102   - compatible
103   - reg
108   - |
109     #include <dt-bindings/interrupt-controller/arm-gic.h>
111         compatible = "qcom,sm6350-tlmm";
123         gpio-controller;
124         #gpio-cells = <2>;
125         interrupt-controller;
126         #interrupt-cells = <2>;
127         gpio-ranges = <&tlmm 0 0 157>;
129         gpio-wo-subnode-state {
131             function = "gpio";
134         uart-w-subnodes-state {
135             rx-pins {
138                 bias-disable;
141             tx-pins {
144                 bias-disable;