bindings/pinctrl/qcom%2Csdx65-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
17     const: qcom,sdx65-tlmm
25   gpio-reserved-ranges:
29   "-state$":
31       - $ref: "#/$defs/qcom-sdx65-tlmm-state"
32       - patternProperties:
33           "-pins$":
34             $ref: "#/$defs/qcom-sdx65-tlmm-state"
38   qcom-sdx65-tlmm-state:
43     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49           List of gpio pins affected by the properties specified in this subnode.
52             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
53 …     - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
60           pins. Functions are only valid for gpio pins.
107                 gpio ]
110       - pins
113   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
116   - compatible
117   - reg
122   - |
123     #include <dt-bindings/interrupt-controller/arm-gic.h>
125         compatible = "qcom,sdx65-tlmm";
127         gpio-controller;
128         #gpio-cells = <2>;
129         gpio-ranges = <&tlmm 0 0 109>;
130         interrupt-controller;
131         #interrupt-cells = <2>;
134         gpio-wo-subnode-state {
136             function = "gpio";
139         uart-w-subnodes-state {
140             rx-pins {
143                 bias-pull-up;
146             tx-pins {
149                 bias-disable;