bindings/pinctrl/qcom%2Csdx55-pinctrl.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SDX55 TLMM block
10   - Vinod Koul <vkoul@kernel.org>
13   Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
17     const: qcom,sdx55-pinctrl
20     description: Specifies the base address and size of the TLMM register space
26   gpio-reserved-ranges:
30   "-state$":
32       - $ref: "#/$defs/qcom-sdx55-tlmm-state"
33       - patternProperties:
34           "-pins$":
35             $ref: "#/$defs/qcom-sdx55-tlmm-state"
39   qcom-sdx55-tlmm-state:
44     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
53             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
54             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
90       - pins
93   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
96   - compatible
97   - reg
102   - |
103     #include <dt-bindings/interrupt-controller/arm-gic.h>
104     tlmm: pinctrl@1f00000 {
105         compatible = "qcom,sdx55-pinctrl";
107         gpio-controller;
108         #gpio-cells = <2>;
109         gpio-ranges = <&tlmm 0 0 108>;
110         interrupt-controller;
111         #interrupt-cells = <2>;
114         serial-state {
117             drive-strength = <8>;
118             bias-disable;