bindings/pinctrl/qcom%2Csc8280xp-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <bjorn.andersson@linaro.org>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sc8280xp-tlmm
28   gpio-reserved-ranges: true
31   "-state$":
33       - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
34       - patternProperties:
35           "-pins$":
36             $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
40   qcom-sc8280xp-tlmm-state:
45     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51           List of gpio pins affected by the properties specified in this
52           subnode.
55             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
56             - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
75                 gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
97       - pins
100   - compatible
101   - reg
106   - |
107     #include <dt-bindings/interrupt-controller/arm-gic.h>
109         compatible = "qcom,sc8280xp-tlmm";
112         gpio-controller;
113         #gpio-cells = <2>;
114         interrupt-controller;
115         #interrupt-cells = <2>;
116         gpio-ranges = <&tlmm 0 0 230>;
118         gpio-wo-subnode-state {
120             function = "gpio";
123         uart-w-subnodes-state {
124             rx-pins {
127                 bias-pull-up;
130             tx-pins {
133                 bias-disable;