bindings/pinctrl/nvidia%2Ctegra124-pinmux.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Thierry Reding <thierry.reding@gmail.com>
11   - Jon Hunter <jonathanh@nvidia.com>
14   Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15   nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21       - const: nvidia,tegra124-pinmux
22       - items:
23           - const: nvidia,tegra132-pinmux
24           - const: nvidia,tegra124-pinmux
28       - description: driver strength and pad control registers
29       - description: pinmux registers
30       - description: MIPI_PAD_CTRL registers
33   "^pinmux(-[a-z0-9-_]+)?$":
36     # pin groups
38       $ref: nvidia,tegra-pinmux-common.yaml
42           $ref: /schemas/types.yaml#/definitions/string-array
59                     ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
117         nvidia,pull-down-strength: true
118         nvidia,pull-up-strength: true
119         nvidia,high-speed-mode: true
120         nvidia,low-power-mode: true
121         nvidia,enable-input: true
122         nvidia,open-drain: true
124         nvidia,io-reset: true
125         nvidia,rcv-sel: true
126         nvidia,drive-type: true
127         nvidia,slew-rate-rising: true
128         nvidia,slew-rate-falling: true
131         - nvidia,pins
136   - compatible
137   - reg
140   - |
141     #include <dt-bindings/clock/tegra124-car.h>
142     #include <dt-bindings/interrupt-controller/arm-gic.h>
143     #include <dt-bindings/pinctrl/pinctrl-tegra.h>
146         compatible = "nvidia,tegra124-pinmux";