bindings/pinctrl/marvell%2Carmada-37xx-pinctrl.txt

1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
34  - functions jtag, gpio
38  - functions sdio, gpio
42  - functions emmc, gpio
46  - functions pwm, led, gpio
50  - functions pwm, led, gpio
54  - functions pwm, led, gpio
58  - functions pwm, led, gpio
62  - functions pmic, gpio
66  - functions pmic, gpio
70  - functions i2c, gpio
74  - functions i2c, gpio
78  - functions spi, gpio
82  - functions spi, gpio
86  - functions spi, gpio
90  - functions onewire, gpio
94  - functions uart, gpio
98  - functions spi, gpio
102  - functions uart, gpio
108  - functions drvbus, gpio
112  - functions drvbus, gpio
116  - functions sdio, gpio
120  - functions mii, gpio
124  - functions pcie, gpio
128  - functions pcie, gpio
132  - functions pcie, gpio
136  - functions smi, gpio
140  - functions ptp, gpio
154 GPIO subnode:
156 Please refer to gpio.txt in this directory for details of gpio-ranges property
157 and the common GPIO bindings used by client devices.
159 Required properties for gpio driver under the gpio subnode:
161 - gpio-controller: Marks the device node as a gpio controller.
162 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
163    second cell specifies GPIO flags, as defined in
164    <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
166 - gpio-ranges: Range of pins managed by the GPIO controller.
178 	gpio {
179 		#gpio-cells = <2>;
180 		gpio-ranges = <&pinctrl_sb 0 0 29>;
181 		gpio-controller;