bindings/pinctrl/lantiq%2Cpinctrl-xway.txt

1 Lantiq XWAY pinmux controller
4 - compatible:	"lantiq,<chip>-pinctrl", where <chip> is:
5 		"ase" (XWAY AMAZON Family)
6 		"danube" (XWAY DANUBE Family)
7 		"xrx100" (XWAY xRX100 Family)
8 		"xrx200" (XWAY xRX200 Family)
9 		"xrx300" (XWAY xRX300 Family)
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
21 pull-up and open-drain
36 Required subnode-properties:
37 - lantiq,groups : An array of strings. Each string contains the name of a group.
39 - lantiq,function: A string containing the name of the function to mux to the
47     spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
51     spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
57     spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
62     spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
69     spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
74     spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
84     stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
89     spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
97     usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
101     spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
106 Required subnode-properties:
107 - lantiq,pins : An array of strings. Each string contains the name of a pin.
110 Optional subnode-properties:
111 - lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
113 - lantiq,open-drain: Boolean, enables open-drain on the defined pin.
116   Pinconf pins can be referenced via the names io0-io31.
119   Pinconf pins can be referenced via the names io0-io31.
122   Pinconf pins can be referenced via the names io0-io55.
125   Pinconf pins can be referenced via the names io0-io49.
128   Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
129 						io13-io19,io23-io27,io34-io36,
130 						io42-io43,io48-io61.
133 	gpio: pinmux@e100b10 {
134 		compatible = "lantiq,danube-pinctrl";
135 		pinctrl-names = "default";
136 		pinctrl-0 = <&state_default>;
138 		#gpio-cells = <2>;
139 		gpio-controller;
143 			stp {
144 				lantiq,groups = "stp";
145 				lantiq,function = "stp";
152 				lantiq,pins = "io4", "io5", "io6"; /* stp */
153 				lantiq,open-drain;