bindings/phy/ti%2Cphy-gmii-sel.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Kishon Vijay Abraham I <kishon@ti.com>
15   two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
20                                                +--------------+
21         +-------------------------------+      |SCM           |
22         |                     CPSW      |      |  +---------+ |
23         |        +--------------------------------+gmii_sel | |
24         |        |                      |      |  +---------+ |
25         |   +----v---+     +--------+   |      +--------------+
26         |   |Port 1..<--+-->GMII/MII<------->
28         |   +--------+  |  +--------+   |
30         |               |  +--------+   |
31         |               |  | RMII   <------->
32         |               +-->        |   |
33         |               |  +--------+   |
35         |               |  +--------+   |
36         |               |  | RGMII  <------->
37         |               +-->        |   |
38         |                  +--------+   |
39         +-------------------------------+
45   of SCM node (scm_conf) and can be attached to each CPSW port node using standard
51       - ti,am3352-phy-gmii-sel
52       - ti,dra7xx-phy-gmii-sel
53       - ti,am43xx-phy-gmii-sel
54       - ti,dm814-phy-gmii-sel
55       - ti,am654-phy-gmii-sel
56       - ti,j7200-cpsw5g-phy-gmii-sel
57       - ti,j721e-cpsw9g-phy-gmii-sel
58       - ti,j784s4-cpsw9g-phy-gmii-sel
63   '#phy-cells': true
65   ti,qsgmii-main-ports:
66     $ref: /schemas/types.yaml#/definitions/uint32-array
68       Required only for QSGMII mode. Array to select the port/s for QSGMII
69       main mode. The size of the array corresponds to the number of QSGMII
73       value corresponding to the QSGMII interface in the array.
81   - if:
86               - ti,dra7xx-phy-gmii-sel
87               - ti,dm814-phy-gmii-sel
88               - ti,am654-phy-gmii-sel
89               - ti,j7200-cpsw5g-phy-gmii-sel
90               - ti,j721e-cpsw9g-phy-gmii-sel
91               - ti,j784s4-cpsw9g-phy-gmii-sel
94         '#phy-cells':
98   - if:
103               - ti,j7200-cpsw5g-phy-gmii-sel
106         ti,qsgmii-main-ports:
112   - if:
117               - ti,j721e-cpsw9g-phy-gmii-sel
118               - ti,j784s4-cpsw9g-phy-gmii-sel
121         ti,qsgmii-main-ports:
128   - if:
134                 - ti,j7200-cpsw5g-phy-gmii-sel
135                 - ti,j721e-cpsw9g-phy-gmii-sel
136                 - ti,j784s4-cpsw9g-phy-gmii-sel
139         ti,qsgmii-main-ports: false
141   - if:
146               - ti,am3352-phy-gmii-sel
147               - ti,am43xx-phy-gmii-sel
150         '#phy-cells':
153             - CPSW port number (starting from 1)
154             - RMII refclk mode
157   - compatible
158   - reg
159   - '#phy-cells'
164   - |
166         compatible = "ti,am3352-phy-gmii-sel";
168         #phy-cells = <2>;