Lines Matching +full:pcie +full:- +full:phy +full:- +full:2
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
22 - socionext,uniphier-nx1-pcie-phy
27 "#phy-cells":
32 maxItems: 2
34 clock-names:
36 maxItems: 2
40 maxItems: 2
42 reset-names:
44 maxItems: 2
48 description: A phandle to system control to set configurations for phy
51 - if:
55 const: socionext,uniphier-pro5-pcie-phy
59 minItems: 2
60 maxItems: 2
61 clock-names:
63 - const: gio
64 - const: link
66 minItems: 2
67 maxItems: 2
68 reset-names:
70 - const: gio
71 - const: link
76 clock-names:
80 reset-names:
84 - compatible
85 - reg
86 - "#phy-cells"
87 - clocks
88 - clock-names
89 - resets
90 - reset-names
95 - |
96 pcie_phy: phy@66038000 {
97 compatible = "socionext,uniphier-ld20-pcie-phy";
99 #phy-cells = <0>;
100 clock-names = "link";
102 reset-names = "link";