bindings/phy/samsung%2Cufs-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Alim Akhtar <alim.akhtar@samsung.com>
13   "#phy-cells":
18       - google,gs101-ufs-phy
19       - samsung,exynos7-ufs-phy
20       - samsung,exynosautov9-ufs-phy
21       - tesla,fsd-ufs-phy
26   reg-names:
28       - const: phy-pma
34   clock-names:
38   samsung,pmu-syscon:
39     $ref: /schemas/types.yaml#/definitions/phandle-array
44         - description: phandle for PMU system controller interface, used to
45                        control pmu registers bits for ufs m-phy
46         - description: offset of the pmu control register
52   - "#phy-cells"
53   - compatible
54   - reg
55   - reg-names
56   - clocks
57   - clock-names
58   - samsung,pmu-syscon
61   - if:
65             const: samsung,exynos7-ufs-phy
71             - description: PLL reference clock
72             - description: symbol clock for input symbol (rx0-ch0 symbol clock)
73             - description: symbol clock for input symbol (rx1-ch1 symbol clock)
74             - description: symbol clock for output symbol (tx0 symbol clock)
76         clock-names:
78             - const: ref_clk
79             - const: rx1_symbol_clk
80             - const: rx0_symbol_clk
81             - const: tx0_symbol_clk
87             - description: PLL reference clock
89         clock-names:
91             - const: ref_clk
96   - |
97     #include <dt-bindings/clock/exynos7-clk.h>
99     ufs_phy: ufs-phy@15571800 {
100         compatible = "samsung,exynos7-ufs-phy";
102         reg-names = "phy-pma";
103         samsung,pmu-syscon = <&pmu_system_controller>;
104         #phy-cells = <0>;
109         clock-names = "ref_clk", "rx1_symbol_clk",