bindings/phy/rockchip%2Crk3588-hdptx-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
15       - rockchip,rk3588-hdptx-phy
22       - description: Reference clock
23       - description: APB clock
25   clock-names:
27       - const: ref
28       - const: apb
30   "#clock-cells":
33   "#phy-cells":
38       - description: PHY reset line
39       - description: APB reset line
40       - description: INIT reset line
41       - description: CMN reset line
42       - description: LANE reset line
43       - description: ROPLL reset line
44       - description: LCPLL reset line
46   reset-names:
48       - const: phy
49       - const: apb
50       - const: init
51       - const: cmn
52       - const: lane
53       - const: ropll
54       - const: lcpll
61   - compatible
62   - reg
63   - clocks
64   - clock-names
65   - "#phy-cells"
66   - resets
67   - reset-names
68   - rockchip,grf
73   - |
74     #include <dt-bindings/clock/rockchip,rk3588-cru.h>
75     #include <dt-bindings/reset/rockchip,rk3588-cru.h>
78       #address-cells = <2>;
79       #size-cells = <2>;
82         compatible = "rockchip,rk3588-hdptx-phy";
84         clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
85         clock-names = "ref", "apb";
86         #phy-cells = <0>;
87         resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
88                  <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
89                  <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
90                  <&cru SRST_HDPTX0_LCPLL>;
91         reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";