bindings/phy/rockchip%2Cpx30-dsi-dphy.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Heiko Stuebner <heiko@sntech.de>
13   "#phy-cells":
18       - rockchip,px30-dsi-dphy
19       - rockchip,rk3128-dsi-dphy
20       - rockchip,rk3368-dsi-dphy
21       - rockchip,rk3568-dsi-dphy
22       - rockchip,rv1126-dsi-dphy
29       - description: PLL reference clock
30       - description: Module clock
32   clock-names:
34       - const: ref
35       - const: pclk
37   power-domains:
43       - description: exclusive PHY reset line
45   reset-names:
47       - const: apb
50   - "#phy-cells"
51   - compatible
52   - reg
53   - clocks
54   - clock-names
55   - resets
56   - reset-names
61   - |
63         compatible = "rockchip,px30-dsi-dphy";
66         clock-names = "ref", "pclk";
68         reset-names = "apb";
69         #phy-cells = <0>;