bindings/phy/rockchip%2Cpcie3-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10   - Heiko Stuebner <heiko@sntech.de>
15       - rockchip,rk3568-pcie3-phy
16       - rockchip,rk3588-pcie3-phy
25   clock-names:
29   data-lanes:
32       (controller-number +1 )
33     $ref: /schemas/types.yaml#/definitions/uint32-array
40   "#phy-cells":
46   reset-names:
47     const: phy
49   rockchip,phy-grf:
51     description: phandle to the syscon managing the phy "general register files"
53   rockchip,pipe-grf:
55     description: phandle to the syscon managing the pipe "general register files"
57   rockchip,rx-common-refclk-mode:
60     $ref: /schemas/types.yaml#/definitions/uint32-array
68   - compatible
69   - reg
70   - rockchip,phy-grf
71   - "#phy-cells"
74   - if:
78             - rockchip,rk3588-pcie3-phy
83         clock-names:
85             - const: pclk
91         clock-names:
93             - const: refclk_m
94             - const: refclk_n
95             - const: pclk
100   - |
101     #include <dt-bindings/clock/rk3568-cru.h>
102     pcie30phy: phy@fe8c0000 {
103       compatible = "rockchip,rk3568-pcie3-phy";
105       #phy-cells = <0>;
109       clock-names = "refclk_m", "refclk_n", "pclk";
111       reset-names = "phy";
112       rockchip,phy-grf = <&pcie30_phy_grf>;