bindings/phy/qcom%2Cmsm8998-qmp-pcie-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, MSM8998)
10   - Vinod Koul <vkoul@kernel.org>
13   The QMP PHY controller supports physical layer functionality for a number of
14   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
18     const: qcom,msm8998-qmp-pcie-phy
22       - description: serdes
27   clock-names:
29       - const: aux
30       - const: cfg_ahb
31       - const: ref
32       - const: pipe
37   reset-names:
39       - const: phy
40       - const: common
42   vdda-phy-supply: true
44   vdda-pll-supply: true
46   "#clock-cells":
49   clock-output-names:
52   "#phy-cells":
56   - compatible
57   - reg
58   - clocks
59   - clock-names
60   - resets
61   - reset-names
62   - vdda-phy-supply
63   - vdda-pll-supply
64   - "#clock-cells"
65   - clock-output-names
66   - "#phy-cells"
71   - |
72     #include <dt-bindings/clock/qcom,gcc-msm8998.h>
74     phy@1c18000 {
75         compatible = "qcom,msm8998-qmp-pcie-phy";
82         clock-names = "aux",
87         clock-output-names = "pcie_0_pipe_clk_src";
88         #clock-cells = <0>;
90         #phy-cells = <0>;
93         reset-names = "phy", "common";
95         vdda-phy-supply = <&vreg_l1a_0p875>;
96         vdda-pll-supply = <&vreg_l2a_1p2>;