Lines Matching +full:otg +full:- +full:port
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
27 In addition to per-lane configuration, USB 3.0 ports may require additional
28 settings on a per-board basis.
30 Pads will be represented as children of the top-level XUSB pad controller
33 PHY bindings, as described by the phy-bindings.txt file in this directory.
37 "port" is typically used to denote the physical USB receptacle. The device
38 tree binding in this document uses the term "port" to refer to the logical
40 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
45 const: nvidia,tegra210-xusb-padctl
52 - description: pad controller reset
56 - description: XUSB pad controller interrupt
58 reset-names:
60 - const: padctl
62 avdd-pll-utmip-supply:
65 avdd-pll-uerefe-supply:
68 dvdd-pex-pll-supply:
71 hvdd-pex-pll-e-supply:
72 description: High-voltage PLLE power supply. Must supply 1.8 V.
97 - description: USB2 tracking clock
99 clock-names:
101 - const: trk
107 usb2-0:
111 "#phy-cells":
119 usb2-1:
123 "#phy-cells":
131 usb2-2:
135 "#phy-cells":
143 usb2-3:
147 "#phy-cells":
161 - description: HSIC tracking clock
163 clock-names:
165 - const: trk
171 hsic-0:
175 "#phy-cells":
183 hsic-1:
187 "#phy-cells":
201 - description: PCIe PLL clock source
203 clock-names:
205 - const: pll
209 - description: PCIe PHY reset
211 reset-names:
213 - const: phy
219 pcie-0:
223 "#phy-cells":
229 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
231 pcie-1:
235 "#phy-cells":
241 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
243 pcie-2:
247 "#phy-cells":
253 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
255 pcie-3:
259 "#phy-cells":
265 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
267 pcie-4:
271 "#phy-cells":
277 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
279 pcie-5:
283 "#phy-cells":
289 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
291 pcie-6:
295 "#phy-cells":
301 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
309 - description: SATA PLL clock source
311 clock-names:
313 - const: pll
317 - description: SATA PHY reset
319 reset-names:
321 - const: phy
327 sata-0:
331 "#phy-cells":
337 enum: [ usb3-ss, sata ]
342 Each port may need additional resources that can be referenced in its
343 port node.
345 The "status" property is used to enable or disable the use of a port.
346 If set to "disabled", the port will not be used on the given board. In
347 order to use the port, this property must be set to "okay".
351 usb2-0:
356 # match on gpio-usb-b-connector or usb-b-connector and cause
363 run the port.
365 enum: [ host, peripheral, otg ]
369 that a port is internal. In the absence of this property
370 the port is considered to be external.
373 usb-role-switch:
375 A boolean property whole presence indicates that the port
376 supports OTG or peripheral mode. If present, the port
380 See ../connector/usb-connector.yaml.
382 vbus-supply:
387 usb-role-switch: [ connector ]
389 usb2-1:
394 # match on gpio-usb-b-connector or usb-b-connector and cause
401 run the port.
403 enum: [ host, peripheral, otg ]
407 that a port is internal. In the absence of this property
408 the port is considered to be external.
411 usb-role-switch:
413 A boolean property whole presence indicates that the port
414 supports OTG or peripheral mode. If present, the port
418 See ../connector/usb-connector.yaml.
420 vbus-supply:
425 usb-role-switch: [ connector ]
427 usb2-2:
432 # match on gpio-usb-b-connector or usb-b-connector and cause
439 run the port.
441 enum: [ host, peripheral, otg ]
445 that a port is internal. In the absence of this property
446 the port is considered to be external.
449 usb-role-switch:
451 A boolean property whole presence indicates that the port
452 supports OTG or peripheral mode. If present, the port
456 See ../connector/usb-connector.yaml.
458 vbus-supply:
463 usb-role-switch: [ connector ]
465 usb2-3:
470 # match on gpio-usb-b-connector or usb-b-connector and cause
477 run the port.
479 enum: [ host, peripheral, otg ]
483 that a port is internal. In the absence of this property
484 the port is considered to be external.
487 usb-role-switch:
489 A boolean property whole presence indicates that the port
490 supports OTG or peripheral mode. If present, the port
494 See ../connector/usb-connector.yaml.
496 vbus-supply:
501 usb-role-switch: [ connector ]
503 hsic-0:
507 vbus-supply:
511 hsic-1:
515 vbus-supply:
519 usb3-0:
525 that a port is internal. In the absence of this property
526 the port is considered to be external.
529 nvidia,usb2-companion:
530 description: A single cell that specifies the physical port
531 number to map this super-speed USB port to. The range of
532 valid port numbers varies with the SoC generation.
536 vbus-supply:
540 usb3-1:
546 that a port is internal. In the absence of this property
547 the port is considered to be external.
550 nvidia,usb2-companion:
551 description: A single cell that specifies the physical port
552 number to map this super-speed USB port to. The range of
553 valid port numbers varies with the SoC generation.
557 vbus-supply:
561 usb3-2:
567 that a port is internal. In the absence of this property
568 the port is considered to be external.
571 nvidia,usb2-companion:
572 description: A single cell that specifies the physical port
573 number to map this super-speed USB port to. The range of
574 valid port numbers varies with the SoC generation.
578 vbus-supply:
582 usb3-3:
588 that a port is internal. In the absence of this property
589 the port is considered to be external.
592 nvidia,usb2-companion:
593 description: A single cell that specifies the physical port
594 number to map this super-speed USB port to. The range of
595 valid port numbers varies with the SoC generation.
599 vbus-supply:
606 - avdd-pll-utmip-supply
607 - avdd-pll-uerefe-supply
608 - dvdd-pex-pll-supply
609 - hvdd-pex-pll-e-supply
612 - |
613 #include <dt-bindings/clock/tegra210-car.h>
614 #include <dt-bindings/gpio/tegra-gpio.h>
615 #include <dt-bindings/interrupt-controller/arm-gic.h>
618 compatible = "nvidia,tegra210-xusb-padctl";
622 reset-names = "padctl";
624 avdd-pll-utmip-supply = <&vdd_1v8>;
625 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
626 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
627 hvdd-pex-pll-e-supply = <&vdd_1v8>;
632 clock-names = "trk";
635 usb2-0 {
637 #phy-cells = <0>;
640 usb2-1 {
642 #phy-cells = <0>;
645 usb2-2 {
647 #phy-cells = <0>;
650 usb2-3 {
652 #phy-cells = <0>;
659 clock-names = "trk";
663 hsic-0 {
665 #phy-cells = <0>;
668 hsic-1 {
670 #phy-cells = <0>;
677 clock-names = "pll";
679 reset-names = "phy";
682 pcie-0 {
683 nvidia,function = "pcie-x1";
684 #phy-cells = <0>;
687 pcie-1 {
688 nvidia,function = "pcie-x4";
689 #phy-cells = <0>;
692 pcie-2 {
693 nvidia,function = "pcie-x4";
694 #phy-cells = <0>;
697 pcie-3 {
698 nvidia,function = "pcie-x4";
699 #phy-cells = <0>;
702 pcie-4 {
703 nvidia,function = "pcie-x4";
704 #phy-cells = <0>;
707 pcie-5 {
708 nvidia,function = "usb3-ss";
709 #phy-cells = <0>;
712 pcie-6 {
713 nvidia,function = "usb3-ss";
714 #phy-cells = <0>;
721 clock-names = "pll";
723 reset-names = "phy";
726 sata-0 {
728 #phy-cells = <0>;
735 usb2-0 {
737 usb-role-switch;
740 compatible = "gpio-usb-b-connector",
741 "usb-b-connector";
742 label = "micro-USB";
744 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
748 usb2-1 {
749 vbus-supply = <&vdd_5v0_rtl>;
753 usb2-2 {
754 vbus-supply = <&vdd_usb_vbus>;
758 usb2-3 {
762 hsic-0 {
766 hsic-1 {
770 usb3-0 {
771 nvidia,usb2-companion = <1>;
774 usb3-1 {
775 nvidia,usb2-companion = <2>;
778 usb3-2 {
782 usb3-3 {