Lines Matching full:lanes
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
25 ports (e.g. PCIe) and the lanes.
88 order to use the pad and any of its lanes, this property must be set
105 lanes:
149 lanes:
177 lanes:
225 lanes:
301 lanes:
537 lanes {
556 lanes {
565 lanes {
579 lanes {
608 lanes {