Lines Matching full:u2

24   u2 port0    0x0800    U2PHY_COM
29   u2 port1    0x1000    U2PHY_COM
34   u2 port2    0x1800    U2PHY_COM
39   u2 port0    0x0000    MISC
48   u2 port1    0x1000    MISC
57   u2 port2    0x2000    MISC
60   SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61   into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
171           - description: internal R efuse for U2 PHY or U3/PCIe PHY
176           Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
190           The value of slew rate calibrate (U2 phy)
197           The selection of VRT reference voltage (U2 phy)
204           The selection of HS_TX TERM reference voltage (U2 phy)
211           The selection of internal resistor (U2 phy)
218           The selection of disconnect threshold (U2 phy)
228           8.3% etc. (U2 phy)