bindings/phy/mediatek%2Cmt7988-xfi-tphy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7988 XFI T-PHY
10   - Daniel Golle <daniel@makrotopia.org>
13   The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
14   used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
15   MediaTek's 10G-capabale MT7988 SoC.
20     const: mediatek,mt7988-xfi-tphy
27       - description: XFI PHY clock
28       - description: XFI register clock
30   clock-names:
32       - const: xfipll
33       - const: topxtal
37       - description: Reset controller corresponding to the phy instance.
39   mediatek,usxgmii-performance-errata:
42       One instance of the T-PHY on MT7988 suffers from a performance
43       problem in 10GBase-R mode which needs a work-around in the driver.
44       This flag enables a work-around adjusting an analog phy setting and
48   "#phy-cells":
52   - compatible
53   - reg
54   - clocks
55   - clock-names
56   - resets
57   - "#phy-cells"
62   - |
63     #include <dt-bindings/clock/mediatek,mt7988-clk.h>
65       #address-cells = <2>;
66       #size-cells = <2>;
69         compatible = "mediatek,mt7988-xfi-tphy";
73         clock-names = "xfipll", "topxtal";
75         mediatek,usxgmii-performance-errata;
76         #phy-cells = <0>;