bindings/phy/mediatek%2Cdsi-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12   - Philipp Zabel <p.zabel@pengutronix.de>
13   - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19     pattern: "^dsi-phy@[0-9a-f]+$"
23       - items:
24           - enum:
25               - mediatek,mt7623-mipi-tx
26           - const: mediatek,mt2701-mipi-tx
27       - items:
28           - enum:
29               - mediatek,mt6795-mipi-tx
30           - const: mediatek,mt8173-mipi-tx
31       - items:
32           - enum:
33               - mediatek,mt8188-mipi-tx
34               - mediatek,mt8195-mipi-tx
35               - mediatek,mt8365-mipi-tx
36           - const: mediatek,mt8183-mipi-tx
37       - const: mediatek,mt2701-mipi-tx
38       - const: mediatek,mt8173-mipi-tx
39       - const: mediatek,mt8183-mipi-tx
46       - description: PLL reference clock
48   clock-output-names:
51   "#phy-cells":
54   "#clock-cells":
57   nvmem-cells:
62   nvmem-cell-names:
64       - const: calibration-data
66   drive-strength-microamp:
74   - compatible
75   - reg
76   - clocks
77   - clock-output-names
78   - "#phy-cells"
79   - "#clock-cells"
84   - |
85     #include <dt-bindings/clock/mt8173-clk.h>
86     dsi-phy@10215000 {
87         compatible = "mediatek,mt8173-mipi-tx";
90         clock-output-names = "mipi_tx0_pll";
91         drive-strength-microamp = <4000>;
92         nvmem-cells = <&mipi_tx_calibration>;
93         nvmem-cell-names = "calibration-data";
94         #clock-cells = <0>;
95         #phy-cells = <0>;