bindings/phy/fsl%2Cimx8qm-lvds-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
10   - Liu Ying <victor.liu@nxp.com>
13   The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15   groups of four data lanes of LVDS data streams. A phase-locked
17   data streams over a fifth LVDS link. Every cycle of the transmit
19   through the two groups of LVDS data streams. Together with the
20   transmit clocks, the two groups of LVDS data streams form two
21   LVDS channels.
23   The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
25   module, as a system controller, contains the PHY's registers.
30       - fsl,imx8qm-lvds-phy
31       - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33   "#phy-cells":
36       Cell allows setting the LVDS channel index of the PHY.
37       Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
42   power-domains:
46   - compatible
47   - "#phy-cells"
48   - clocks
49   - power-domains
54   - |
55     #include <dt-bindings/firmware/imx/rsrc.h>
56     phy {
57         compatible = "fsl,imx8qm-lvds-phy";
58         #phy-cells = <1>;
60         power-domains = <&pd IMX_SC_R_LVDS_0>;