bindings/phy/fsl%2Cimx8qm-hsio.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Richard Zhu <hongxing.zhu@nxp.com>
15       - fsl,imx8qm-hsio
16       - fsl,imx8qxp-hsio
19       - description: Base address and length of the PHY block
20       - description: HSIO control and status registers(CSR) of the PHY
21       - description: HSIO CSR of the controller bound to the PHY
22       - description: HSIO CSR for MISC
24   reg-names:
26       - const: reg
27       - const: phy
28       - const: ctrl
29       - const: misc
31   "#phy-cells":
43   clock-names:
47   fsl,hsio-cfg:
52       +---------------------------------------+
54       |------------------|--------------------|
56       |------------------|------|------|------|
57       | pciea-x2-sata    | PCIEA| PCIEA| SATA |
58       |------------------|------|------|------|
59       | pciea-x2-pcieb   | PCIEA| PCIEA| PCIEB|
60       |------------------|------|------|------|
61       | pciea-pcieb-sata | PCIEA| PCIEB| SATA |
62       +---------------------------------------+
64     enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
65     default: pciea-pcieb-sata
67   fsl,refclk-pad-mode:
78   power-domains:
83   - compatible
84   - reg
85   - reg-names
86   - "#phy-cells"
87   - clocks
88   - clock-names
89   - fsl,hsio-cfg
92   - if:
97               - fsl,imx8qxp-hsio
100         clock-names:
102             - const: pclk0
103             - const: apb_pclk0
104             - const: phy0_crr
105             - const: ctl0_crr
106             - const: misc_crr
107         power-domains:
110   - if:
115               - fsl,imx8qm-hsio
118         clock-names:
120             - const: pclk0
121             - const: pclk1
122             - const: apb_pclk0
123             - const: apb_pclk1
124             - const: pclk2
125             - const: epcs_tx
126             - const: epcs_rx
127             - const: apb_pclk2
128             - const: phy0_crr
129             - const: phy1_crr
130             - const: ctl0_crr
131             - const: ctl1_crr
132             - const: ctl2_crr
133             - const: misc_crr
134         power-domains:
140   - |
141     #include <dt-bindings/clock/imx8-clock.h>
142     #include <dt-bindings/clock/imx8-lpcg.h>
143     #include <dt-bindings/firmware/imx/rsrc.h>
144     #include <dt-bindings/phy/phy-imx8-pcie.h>
147         compatible = "fsl,imx8qxp-hsio";
152         reg-names = "reg", "phy", "ctrl", "misc";
158         clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";
159         power-domains = <&pd IMX_SC_R_SERDES_1>;
160         #phy-cells = <3>;
161         fsl,hsio-cfg = "pciea-pcieb-sata";
162         fsl,refclk-pad-mode = "input";