bindings/phy/airoha%2Cen7581-pcie-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 PCI-Express PHY
10   - Lorenzo Bianconi <lorenzo@kernel.org>
13   The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
17     const: airoha,en7581-pcie-phy
21       - description: PCIE analog base address
22       - description: PCIE lane0 base address
23       - description: PCIE lane1 base address
24       - description: PCIE lane0 detection time base address
25       - description: PCIE lane1 detection time base address
26       - description: PCIE Rx AEQ base address
28   reg-names:
30       - const: csr-2l
31       - const: pma0
32       - const: pma1
33       - const: p0-xr-dtime
34       - const: p1-xr-dtime
35       - const: rx-aeq
37   "#phy-cells":
41   - compatible
42   - reg
43   - reg-names
44   - "#phy-cells"
49   - |
50     #include <dt-bindings/phy/phy.h>
53         #address-cells = <2>;
54         #size-cells = <2>;
56         phy@11e80000 {
57             compatible = "airoha,en7581-pcie-phy";
58             #phy-cells = <0>;
65             reg-names = "csr-2l", "pma0", "pma1",
66                         "p0-xr-dtime", "p1-xr-dtime",
67                         "rx-aeq";