bindings/perf/riscv%2Cpmu.yaml

1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10   - Atish Patra <atishp@rivosinc.com>
13   The SBI PMU extension allows supervisor software to configure, start and
18     The platform must provide information about PMU event to counter mappings
19     either via device tree or another way, specific to the platform.
20     Without the event to counter mappings, the SBI PMU extension cannot be used.
25     or another way, specific to the platform.
26     The exact value to be written to MHPMEVENTx is completely dependent on the
31       https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
37   riscv,event-to-mhpmevent:
38     $ref: /schemas/types.yaml#/definitions/uint32-matrix
40       Represents an ONE-to-ONE mapping between a PMU event and the event
41       selector value that the platform expects to be written to the MHPMEVENTx
48         - description: event_idx, a 20-bit wide encoding of the event type and
49             code. Refer to the SBI specification for a complete description of
51         - description: upper 32 bits of the event selector value for MHPMEVENTx
52         - description: lower 32 bits of the event selector value for MHPMEVENTx
54   riscv,event-to-mhpmcounters:
55     $ref: /schemas/types.yaml#/definitions/uint32-matrix
57       Represents a MANY-to-MANY mapping between a range of events and all the
58       MHPMCOUNTERx in a bitmap format that can be used to monitor these range
64         - description: first event_idx of the range of events
65         - description: last event_idx of the range of events
66         - description: bitmap of MHPMCOUNTERx for this event
68   riscv,raw-event-to-mhpmcounters:
69     $ref: /schemas/types.yaml#/definitions/uint32-matrix
71       Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
72       and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
81         - description:
83         - description:
85         - description:
87         - description:
89         - description:
93   riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
96   - compatible
101   - |
104         riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105         riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
109         riscv,raw-event-to-mhpmcounters =
112             /* For event ID 0-4 */
114             /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
118   - |
121 …* https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6…
123      * This example also binds standard SBI PMU hardware IDs to U74 PMU event
125      * can be bound to a single perf ID.
130           riscv,event-to-mhpmevent =
131               /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
133               /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
135               /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
137               /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
139               /* L1D_READ_MISS -> Data cache miss or MMIO access */
141               /* L1D_WRITE_ACCESS -> Data cache write-back */
143               /* L1I_READ_ACCESS -> Instruction cache miss */
145               /* LL_READ_MISS -> UTLB miss */
147               /* DTLB_READ_MISS -> Data TLB miss */
149               /* ITLB_READ_MISS-> Instruction TLB miss */
151           riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
157           riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,