bindings/pci/xilinx-versal-cpm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13   - $ref: /schemas/pci/pci-host-bridge.yaml#
18       - xlnx,versal-cpm-host-1.00
19       - xlnx,versal-cpm5-host
23       - description: CPM system level control and status registers.
24       - description: Configuration space region and bridge registers.
25       - description: CPM5 control and status registers.
28   reg-names:
30       - const: cpm_slcr
31       - const: cfg
32       - const: cpm_csr
38   msi-map:
45   "#interrupt-cells":
48   interrupt-controller:
49     description: Interrupt controller node for handling legacy PCI interrupts.
54       "#address-cells":
57       "#interrupt-cells":
60       interrupt-controller: true
63   - reg
64   - reg-names
65   - "#interrupt-cells"
66   - interrupts
67   - interrupt-map
68   - interrupt-map-mask
69   - bus-range
70   - msi-map
71   - interrupt-controller
76   - |
79                #address-cells = <2>;
80                #size-cells = <2>;
82                        compatible = "xlnx,versal-cpm-host-1.00";
84                        #address-cells = <3>;
85                        #interrupt-cells = <1>;
86                        #size-cells = <2>;
88                        interrupt-parent = <&gic>;
89                        interrupt-map-mask = <0 0 0 7>;
90                        interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
94                        bus-range = <0x00 0xff>;
97                        msi-map = <0x0 &its_gic 0x0 0x10000>;
100                        reg-names = "cpm_slcr", "cfg";
101                        pcie_intc_0: interrupt-controller {
102                                #address-cells = <0>;
103                                #interrupt-cells = <1>;
104                                interrupt-controller;
109                        compatible = "xlnx,versal-cpm5-host";
111                        #address-cells = <3>;
112                        #interrupt-cells = <1>;
113                        #size-cells = <2>;
115                        interrupt-parent = <&gic>;
116                        interrupt-map-mask = <0 0 0 7>;
117                        interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
121                        bus-range = <0x00 0xff>;
124                        msi-map = <0x0 &its_gic 0x0 0x10000>;
128                        reg-names = "cpm_slcr", "cfg", "cpm_csr";
130                        pcie_intc_1: interrupt-controller {
131                                #address-cells = <0>;
132                                #interrupt-cells = <1>;
133                                interrupt-controller;